The present invention relates to an adder circuit and, more particularly, to a parallel adder circuit.
With a multidigit parallel adder circuit which is to be operated at a high speed, it is necessary to significantly shorten the propagation delay time between a carry input and a carry output of an adder circuit.
A conventional parallel adder circuit is constituted by a full adder as shown in, e.g., FIG. 1. In FIG. 1, A.sub.i denotes an addend input; B.sub.i is an augend input; C.sub.i-1 is a carry input from the preceding stage; S.sub.i a sum output; C.sub.i is a carry output to the succeeding stage; reference numerals 11 and 12 indicate EX-OR (EXCLUSIVE OR) gate circuits; and reference numerals 13, 14 and 15 indicate NAND gate circuits.
In the full adder shown in FIG. 1, a propagation delay time corresponding to two stages of the NAND gate circuits is involved in generating the carry signal; furthermore, the time delay corresponding to one stage of the EX-OR gate circuit occurs until the sum output S.sub.i is obtained.
A full adder to improve such drawbacks is shown in FIG. 2 and is disclosed in Japanese Laid-Open Patent Application Nos. 147235/1981 and 147236/1981. This adder comprises: a control circuit including an OR gate circuit 16, a NAND gate circuit 17 and an inverter 18; an input circuit having an NAND gate circuit 19; and a switching circuit including an inverter 20 and clocked inverters S.sub.1 to S.sub.4. The control circuit is arranged to provide a control signal .phi. which becomes high when an addend input is equal to an augend input. A control signal .phi. is complementary to signal .phi.. On the other hand, the clocked inverters S.sub.1 and S.sub.4 operate when the control signal .phi. is high, while the clocked inverters S.sub.2 and S.sub.3 operate when the inverted control signal .phi. is high.
The arrangement of the full adder in FIG. 2 is very simple and the maximum time delay in the carry propagation is involved only with the switching circuit including the inverter 20. Also, the clocked inverters S.sub.1 to S.sub.4 whose operating speed is faster than an NAND gate circuit are used as the switching circuit. Consequently, this full adder is very advantageous for a high speed operation.
However, even in such a full adder, a maximum time delay for the carry propagation occurs due to the inverter 20 and clocked inverter S.sub.1. Therefore, a conventional multistage adder circuit having such full adders as described above does not have satisfactory carry propagation.